--=====================================================
-- Проект 44. Простой калькулятор на 7-сегментном выводе
-- Два однозначных числа и операция; результат
-- сразу подан на дешифратор индикатора.
--=====================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_calc is
    port (
        a, b    : in  std_logic_vector(3 downto 0);       -- операнды 0..9
        op      : in  std_logic_vector(1 downto 0);        -- 00 + 01 - 10 x
        seg_hi  : out std_logic_vector(6 downto 0);        -- старший разряд
        seg_lo  : out std_logic_vector(6 downto 0);        -- младший разряд
        overflow: out std_logic
    );
end entity simple_calc;

architecture rtl of simple_calc is
    function to_seg(d : integer) return std_logic_vector is
        type t is array (0 to 9) of std_logic_vector(6 downto 0);
        constant TAB : t := (
            "1000000","1111001","0100100","0110000","0011001",
            "0010010","0000010","1111000","0000000","0010000");
    begin
        return TAB(d);
    end function;

    signal res : integer range 0 to 99;
    signal ov  : std_logic;
begin
    process (a, b, op)
        variable ai, bi, r : integer;
    begin
        ai := to_integer(unsigned(a));
        bi := to_integer(unsigned(b));
        ov <= '0';
        case op is
            when "00" => r := ai + bi;
            when "01" =>
                if ai >= bi then r := ai - bi; else r := 0; ov <= '1'; end if;
            when "10" => r := ai * bi;
            when others => r := 0;
        end case;
        if r > 99 then
            r  := 99;
            ov <= '1';
        end if;
        res <= r;
    end process;

    seg_hi   <= to_seg(res / 10);
    seg_lo   <= to_seg(res mod 10);
    overflow <= ov;
end architecture rtl;